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José Roberto Pérez Andrade
José Roberto Pérez Andrade
Ingeniero de Validación, Intel
Verified email at tamps.cinvestav.mx
Title
Cited by
Cited by
Year
A versatile linear insertion sorter based on an FIFO scheme
R Perez-Andrade, R Cumplido, C Feregrino-Uribe, FM Del Campo
Microelectronics Journal 40 (12), 1705-1713, 2009
522009
A versatile hardware architecture for a constant false alarm rate processor based on a linear insertion sorter
R Perez-Andrade, R Cumplido, C Feregrino-Uribe, FM Del Campo
Digital Signal Processing 20 (6), 1733-1747, 2010
192010
A multi-cycle fixed point square root module for FPGAs
FM del Campo, A Morales-Reyes, R Perez-Andrade, R Cumplido, ...
IEICE Electronics Express 9 (11), 971-977, 2012
132012
Processor arrays generation for matrix algorithms used in embedded platforms implemented on FPGAs
R Perez-Andrade, C Torres-Huitzil, R Cumplido
Microprocessors and Microsystems 39 (7), 576-588, 2015
72015
A system on a programmable chip architecture for data-dependent superimposed training channel estimation
F Martín del Campo, R Cumplido, R Perez-Andrade, AG Orozco-Lugo
International Journal of Reconfigurable Computing 2009, 2009
72009
A versatile hardware architecture for a CFAR detector based on a linear insertion sorter
R Perez-Andrade, R Cumplido, C Feregrino-Uribe, FM Del Campo
2008 International Conference on Field Programmable Logic and Applications …, 2008
72008
Towards symbolic run-time reconfiguration in tightly-coupled processor arrays
S Boppu, F Hannig, J Teich, R Perez-Andrade
2011 International Conference on Reconfigurable Computing and FPGAs, 392-397, 2011
52011
On a hybrid and general control scheme for algorithms represented as a polytope
R Perez-Andrade, C Torres-Huitzil, R Cumplido, JM Campos
2011 IEEE International Symposium on Parallel and Distributed Processing …, 2011
32011
On an external memory scheme for processor arrays
R Perez-Andrade, C Torres-Huitzil, R Cumplido, JM Campos
IEICE Electronics Express 10 (14), 2013
22013
A SOPC Architecture for Data-dependent Superimposed Training Channel Estimation
FM del Campo, R Cumplido, R Perez-Andrade, AG Orozco-Lugo
Reconfigurable Communicationcentric Systems-on-Chip (ReCoSoC), 2008
22008
A parallelization methodology for reconfigurable systems applied to edge detection
JM Campos, R Cumplido, C Feregrino-Uribe, R Pérez-Andrade
2013 8th International Workshop on Reconfigurable and Communication-Centric …, 2013
12013
Processor arrays generation for matrix algorithms used in embedded platforms
R Perez-Andrade, C Torres-Huitzil, R Cumplido, JM Campos
2013 International Conference on Reconfigurable Computing and FPGAs …, 2013
2013
Hybrid Architecture for Data-dependent Superimposed Training in Digital Receivers
FM del Campo, R Cumplido, R Perez-Andrade, AG Orozco-Lugo
2008 International Conference on Reconfigurable Computing and FPGAs, 355-360, 2008
2008
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Articles 1–13