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José Luis García Gervacio
José Luis García Gervacio
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Timing performance of nanometer digital circuits under process variations
V Champac, JG Gervacio
Springer International Publishing, 2018
292018
PSEM Approximations for Both Branches of Lambert W Function with Applications
H Vazquez-Leal, MA Sandoval-Hernandez, JL Garcia-Gervacio, ...
Discrete Dynamics in Nature and Society 2019 (1), 8267951, 2019
222019
SCADA system design: A proposal for optimizing a production line
JAR Carmona, JCM Benítez, JL García-Gervacio
2016 International Conference on Electronics, Communications and Computers …, 2016
182016
Testing of resistive opens in CMOS latches and flip-flops
VH Champac, A Zenteno, JL Garcia
European Test Symposium (ETS'05), 34-40, 2005
182005
Direct application of Padé approximant for solving nonlinear differential equations
H Vazquez-Leal, B Benhammouda, U Filobello-Nino, A Sarmiento-Reyes, ...
SpringerPlus 3, 1-11, 2014
172014
A design methodology for logic paths tolerant to local intra-die variations
D Iparraguirre-Cárdenas, JL Garcia-Gervacio, V Champac
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on, 596-599, 2008
122008
Small-delay defects detection under process variation using Inter-Path Correlation
FJ Galarza-Medina, JL García-Gervacio, V Champac, A Orailoglu
2012 IEEE 30th VLSI Test Symposium (VTS), 127-132, 2012
102012
TCAD analysis and modeling for NBTI mechanism in FinFET transistors
A Herrera-Moreno, JL García-Gervacio, H Villacorta-Minaya, ...
IEICE Electronics Express 15 (14), 20180502-20180502, 2018
92018
Direct application of Pade approximant for solving nonlinear differential equations. SpringerPlus, 3 (563)
H Vazquez-Leal, B Benhammouda, U Filobello-Nino, A Darmiento-Reyes, ...
72014
Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICs
JL García-Gervacio, V Champac
Test Symposium (ETS), 2010 15th IEEE European, 126-131, 2010
72010
Computing the Detection Probability for Small Delay Defects of Nanometer ICs
JL García-Gervacio, V Champac
Journal of Electronic Testing, 1-12, 2011
42011
A methodology to compute the statistical fault coverage of small delays due to opens
JL Garcia-Gervacio, V Champac
2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 1211 …, 2009
42009
Detectability analysis of small delays due to resistive opens considering process variations
JL Garcia-Gervacio, V Champac
On-Line Testing Symposium, 2009. IOLTS 2009. 15th IEEE International, 195-197, 2009
42009
Low VDD and body bias conditions for testing bridge defects in the presence of process variations
H Villacorta, J Garcia-Gervacio, J Segura, V Champac
Microelectronics Journal 46 (5), 398-403, 2015
32015
Screening small-delay defects using inter-path correlation to reduce reliability risk
JL García-Gervacio, A Nocua, V Champac
Microelectronics Reliability 55 (6), 1005-1011, 2015
32015
Process Variations
V Champac, J Garcia Gervacio, V Champac, J Garcia Gervacio
Timing Performance of Nanometer Digital Circuits Under Process Variations, 41-69, 2018
22018
Testbed module for UHF passive RFID tags
LF Lagunes-Aranda, AG Martínez-López, J Martínez-Castillo, ...
2016 IEEE International Engineering Summit, II Cumbre Internacional de las …, 2016
22016
Possibilities of defect-size magnification for testing resistive-opens in nanometer technologies
JL García-Gervacio, J Martínez-Castillo, V Champac
2014 15th Latin American Test Workshop-LATW, 1-6, 2014
22014
Voltage Regulation System for UHF RFID Tags
JLG Gervacio, ALH May, GZ Mejía, JM Castillo, AD Sánchez
2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2013
22013
Designing with FinFETs and Process Variation Impact
V Champac, J Garcia Gervacio, V Champac, J Garcia Gervacio
Timing Performance of Nanometer Digital Circuits Under Process Variations …, 2018
12018
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