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Laurent Fesquet
Laurent Fesquet
Grenoble INP - Université Grenoble Alpes
Dirección de correo verificada de univ-grenoble-alpes.fr
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A new class of asynchronous A/D converters based on time quantization
E Allier, G Sicard, L Fesquet, M Renaudin
Ninth International Symposium on Asynchronous Circuits and Systems, 2003 …, 2003
2852003
A very high speed true random number generator with entropy assessment
A Cherkaoui, V Fischer, L Fesquet, A Aubert
Cryptographic Hardware and Embedded Systems-CHES 2013: 15th International …, 2013
1422013
Implementing asynchronous circuits on LUT based FPGAs
QT Ho, JB Rigaud, L Fesquet, M Renaudin, R Rolland
Field-Programmable Logic and Applications: Reconfigurable Computing Is Going …, 2002
1092002
Asynchronous FIR filters: towards a new digital processing chain
F Aeschlimann, E Allier, L Fesquet, M Renaudin
10th International Symposium on Asynchronous Circuits and Systems, 2004 …, 2004
1072004
A self-timed ring based true random number generator
A Cherkaoui, V Fischer, A Aubert, L Fesquet
2013 IEEE 19th international symposium on asynchronous circuits and systems …, 2013
882013
Adaptive rate filtering a computationally efficient signal processing approach
SM Qaisar, L Fesquet, M Renaudin
Signal Processing 94, 620-630, 2014
762014
Asynchronous level crossing analog to digital converters
E Allier, G Sicard, L Fesquet, M Renaudin
Measurement 37 (4), 296-309, 2005
682005
High-level time-accurate model for the design of self-timed ring oscillators
J Hamon, L Fesquet, B Miscopein, M Renaudin
2008 14th IEEE international symposium on asynchronous circuits and systems …, 2008
622008
Technology mapping for area optimized quasi delay insensitive circuits
B Folco, V Brégier, L Fesquet, M Renaudin
Vlsi-Soc: From Systems To Silicon: Proceedings of IFIP TC 10, WG 10.5 …, 2007
602007
FPGA architecture for multi-style asynchronous logic [full-adder example]
N Huot, H Dubreuil, L Fesquet, M Renaudin
Design, Automation and Test in Europe, 32-33, 2005
512005
Programmable/stoppable oscillator based on self-timed rings
E Yahya, O Elissati, H Zakaria, L Fesquet, M Renaudin
2009 15th IEEE Symposium on Asynchronous Circuits and Systems, 3-12, 2009
462009
Spectral analysis of a signal driven sampling scheme
SM Qaisar, L Fesquet, M Renaudin
2006 14th European Signal Processing Conference, 1-5, 2006
412006
Comparison of self-timed ring and inverter ring oscillators as entropy sources in FPGAs
A Cherkaoui, V Fischer, A Aubert, L Fesquet
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2012
382012
PSL-based online monitoring of digital systems
D Borrione, M Liu, P Ostier, L Fesquet
Applications of Specification and Design Languages for SoCs: Selected papers …, 2006
352006
Adaptive rate sampling and filtering based on level crossing sampling
S Mian Qaisar, L Fesquet, M Renaudin
EURASIP Journal on Advances in Signal Processing 2009, 1-12, 2009
342009
Static timing analysis of asynchronous bundled-data circuits
G Gimenez, A Cherkaoui, G Cogniard, L Fesquet
2018 24th IEEE International Symposium on Asynchronous Circuits and Systems …, 2018
332018
Computationally efficient adaptive rate sampling and filtering
SM Qaisar, L Fesquet, M Renaudin
2007 15th European Signal Processing Conference, 2139-2143, 2007
332007
IIR digital filtering of non-uniformly sampled signals via state representation
L Fesquet, B Bidégaray-Fesquet
Signal Processing 90 (10), 2811-2821, 2010
302010
On-line assertion-based verification with proven correct monitors
D Borrione, M Liu, K Morin-Allory, P Ostier, L Fesquet
2005 International Conference on Information and Communication Technology …, 2005
292005
An adaptive resolution computationally efficient short-time Fourier transform
SM Qaisar, L Fesquet, M Renaudin
Journal of Electrical and Computer Engineering 2008, 2008
272008
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