| Training feedforward neural networks using hybrid particle swarm optimization and gravitational search algorithm SA Mirjalili, SZM Hashim, HM Sardroudi Applied Mathematics and Computation 218 (22), 11125-11137, 2012 | 593 | 2012 |
| A new approach for relational database watermarking using image HM Sardroudi, S Ibrahim 5th International Conference on Computer Sciences and Convergence …, 2010 | 29 | 2010 |
| Probing approximate TMR in error resilient applications for better design tradeoffs T Arifeen, AS Hassan, H Moradian, JA Lee 2016 Euromicro Conference on Digital System Design (DSD), 637-640, 2016 | 26 | 2016 |
| Input vulnerability‐aware approximate triple modular redundancy: higher fault coverage, improved search space, and reduced area overhead T Arifeen, AS Hassan, H Moradian, JA Lee Electronics Letters 54 (15), 934-936, 2018 | 17 | 2018 |
| FPGA implementation of convolutional neural network based on stochastic computing D Kim, MS Moghaddam, H Moradian, H Sim, J Lee, K Choi 2017 international conference on field programmable technology (ICFPT), 287-290, 2017 | 14 | 2017 |
| Self-repairing radix-2 signed-digit adder with multiple error detection, correction, and fault localization H Moradian, JA Lee, A Hashmi Microelectronics Reliability 63, 256-266, 2016 | 14 | 2016 |
| Generation methodology for good-enough approximate modules of ATMR AS Hassan, T Arifeen, H Moradian, JA Lee Journal of Electronic Testing 34, 651-665, 2018 | 11 | 2018 |
| Robust Database Watermarking Technique over Numerical Data H Moradian Sardroudi, S Ibrahim, Z Omid Journal of Communications and Information Sciences (JCIS) 1 (1), 30-40, 2011 | 7* | 2011 |
| Efficient low-cost fault-localization and self-repairing radix-2 signed-digit adders applying the self-dual concept H Moradian, JA Lee, J Yu Journal of Signal Processing Systems 88, 297-309, 2017 | 6 | 2017 |
| Low-Cost Fault Localization and Error Correction for a Signed Digit Adder Design Utilizing the Self-Dual Concept H Moradian, JA Lee 2015 Euromicro Conference on Digital System Design, 276-279, 2015 | 3 | 2015 |
| Fault localization and error correction method for self-checking binary signed-digit adder and digital logic circuit for the method JA Lee, H Moradian US Patent 10,133,624, 2018 | | 2018 |
| Reconfigurable Multi-Input Adder Design for Deep Neural Network Accelerators H Moradian, S Jo, K Choi 2018 International SoC Design Conference (ISOCC), 212-213, 2018 | | 2018 |
| Area and Power Efficient Adders for Digital Processing Systems H Moradian, T Arifeen, AS Hassan, JA Lee JCCI 2017, 2017 | | 2017 |
| Accuracy Analyzing of Approximate Adders Based on Input Data Range in IoT H Moradian, T Arifeen, AS Hassan, JA Lee JCCI 2017, 2017 | | 2017 |
| Further Simplification of Approximate Adders Using Input Data Ranges in IoT H Moradian, T Arifeen, AS Hassan, JA Lee DATE, IP7 Ten Cent Chip Challenge - Interactive Presentations, 2017 | | 2017 |
| FPGA Based Low Power Design of An FIR Filter Using Polyphase Decomposition AS Hassan, A Hassan, T Arifeen, H Moradien, JA Lee 한국정보과학회 학술발표논문집, 1547-1549, 2016 | | 2016 |
| Comparative Study of LSB-Based Steganography Algorithms O Zanganeh, S Ibrahim, H Moradian Sardroudi 3rd International Graduate Conference on Engineering, Science & Humanities …, 2010 | | 2010 |
